library verilog;
use verilog.vl_types.all;
entity RPMCounter is
    port(
        clk             : in     vl_logic;
        pulse           : in     vl_logic;
        dig1            : out    vl_logic_vector(3 downto 0);
        dig2            : out    vl_logic_vector(3 downto 0);
        dig3            : out    vl_logic_vector(3 downto 0)
    );
end RPMCounter;
